Efficient Hardware Design for a Narrowband Channelizer Using Multi-Stage Digital Frequency Conversion

We propose a multi-stage Digital Frequency Converter (DFC) channelizer for PSR narrowband repeaters and demonstrate a scalable FPGA implementation. The channelizer interleaves DDS-based complex mixing between decimation stages. By time-division multiplexing the DDS and a single complex multiplier at each stage, multiple channels share the same hardware, improving resource efficiency. A 16-channel bank (4×4) is realized, and multi-bank composition enables multiples-of-16 channel scalability while keeping the shared decimation/interpolation path as a fixed cost. The PSR repeater was implemented on an AMD Xilinx UltraScale+ RFSoC and verified with a spectrum analyzer. The prototype simultaneously processes 16 channels of 12.5-kHz signals and meets the specified in-band/stop-band requirements, confirming real-time operation with low FPGA utilization and straightforward scalability.