Automated Low-Noise Amplifier Design Methodology for Wireless Sensor Nodes
Abstract
This paper outlines a detailed design methodology for Low-Noise Amplifiers (LNAs), using a 65nm CMOS process node. The main target of this work is to simplify and accelerate the LNA design cycle without compromising on performance. The provided simulation results confirm the efficacy of the proposed methodology, deriving an LNA with S1115dB, S12
Fields of Study & Subjects
Radio Frequency Integrated Circuit Design
Analog and Mixed-Signal Circuit Design
Low-power high-performance VLSI design
Publication details
- Journal / source
- Emerging Tech Conference Edge Intelligence
- Pages
- 160–165
- Publication date
- 10 March 2026
- Language
- EN