Crosstalk-Driven and Timing-Driven Routing in a 28 nm ASIC: A Comparative Study

Interconnect coupling capacitance has become a major problem in deep-submicrometer 28 nm ASIC designs both in signal integrity and timing closure. Traditional routing methods, which mainly rely on wire-length and routability are not effective in dealing with delay and noise caused by crosstalk. This paper introduces a crosstalk-based and timing-based routing architecture which is the model that crosstalk-induced congestion propagates spatially among neighboring nets. Crosstalk-conscious, static timing analysis is used, including timing window overlap to do a critical net identification and prioritization. The proposed iterative routing technique incorporates the use of net reordering, wire spacing, shielding, buffering and physical separation as a solution to counter the effects of coupling. Experimental results on industrial benchmark circuits show that worst negative slack is greatly improved and signal integrity violations are also greatly reduced with only small overhead costs in area and routing congestion which leads to improved timing robustness and reliability in 28 nm VLSI layouts.