Design Rule Violations Optimization During Physical Routing

Maximum capacitance, maximum transition, and maximum fanout electrical design rule violation (DRVs) are major impediments in the contemporary ASIC physical-design, which directly affect signal integrity, timing performance, and manufacturability. Conventional sequential optimization flows can result into iterative regressions and extend design closure and risk frequency targets. The current paper describes an ICC2-based co-optimization strategy that jointly works on electrical DRVs and timing closure in physical routing. The flow combines both DRV-aware and timing-driven control into a single optimization cycle, using net splitting, driver upsizing, buffer tree insertion, and layer promotion. As shown in experimental data on a 28 nm ASIC block with approximately 1.2M instances, zero convergence to DRVs is obtained and timing closure is obtained at 454.5 MHz with 2.2 ns cycle. Worst Negative Slack had improved to +0.03 ns, Total Negative Slack had been reduced to 0.02 ns and the number of closure iterations had significantly decreased (almost 40 per cent) compared with sequential methods. The paper also presents the scalability to hierarchical SoC designs, voltage island integration, and further AI-assisted routing strategies.