Macro-Aware Keepout Margin Optimization for Timing and Routability

The strategic integration of Intellectual Property (IP) macros between soft IPs and hard IPs is the base framework in the attainment of design timing closure and improved performance. Since the main limitations to signal timing, power distribution and silicon area efficiency are determined by these high-density blocks, their location is a critical factor in determining chip performance. Another major drawback of the traditional workflows is the physical integration that is not optimal, namely the definition of keepout margins. Small keepout margins around macros can easily lead to routing congestion where too much standard cell density around macro boundaries causes a lot of congestion. To reduce this, macro placement applies flyline analysis to chart logical connectivity, and avoids congestion by making sure the orientation is proper, keepout margins are mathematically sized to fit all the tracks, and has a huge impact on the QoR and the timeline to tape-out.