On-Chip Power Regulator

Modern SoC and IoT devices demand compact and reliable on-chip voltage regulation, while conventional LDO designs suffer from stability, quiescent power, and bulky external capacitor requirements. This study give a new perspective to overcome this challenge by developing a dual-NMOS, capacitor-less LDO architecture employing a simple CMOS inverter-based control method that eliminates the need for an error amplifier, and automatically adapts to load variations. The design is evaluated through LT-spice simulations using a 180 nm CMOS setup, including transient, DC, and AC analyses of the LDO and its integrated op-amp. It reaches a stable 1.2 V output and shows strong loop stability with an op-amp gain of ~70 dB at a 132? phase margin. Moreover, it offers low quiescent current and clean transient behavior without any off-chip capacitors. These are indications of how the proposed design can achieve great efficiency and stability with minimum Silicon area, suitable for next-generation SoC and sensor power-management systems.