A REFINED AND EFFICIENT ONE-BIT MODIFIED HYBRID FULL ADDER FOR SWIFT AND FRUGAL DIGITAL COMPUTATION

In modern VLSI circuits, logical operations are fundamental to system performance. The full adder circuit, in particular, serves a critical role in applications such as digital signal processors, microcontrollers, microprocessors, application-specific ICs (ASICs), and data processing units. With the ongoing trends of device scaling and portability, there is a growing demand for digital circuits that offer low power consumption, high speed, and minimal silicon area. Consequently, the design and optimization of low-power, high-performance adders are of significant interest, as any enhancement to the full adder directly impacts overall system efficiency. Gate Diffusion Input (GDI) emerges as an advanced technique for low-power digital IC design, offering reductions in power consumption, delay, and transistor count compared to conventional CMOS implementations. This paper presents a detailed performance analysis of a GDI-based 1-bit full adder for lowpower applications. The circuit’s behavior, in terms of average power and propagation delay, is analyzed in the nanometer regime, making it suitable for modern low-power applications. All simulations are performed using the BPTM model and carried out with Tanner EDA tools on 45nm technology