Cryogenic Embedded Memory Benchmark: SRAM Vs. DRAM In 45- Nm CMOS

Quantum computing and cryogenic electronic systems require embedded memories that can operate reliably at extremely low temperatures around 4.2 Kelvin.Integrating cryo-CMOS memories within quantum processors is critical to reduce wiring complexity and thermal loads as processor scales increase.This work presents a thorough benchmarking study of embedded SRAM and DRAM fabricated using a 45-nm CMOS process under cryogenic conditions.Key performance parameters evaluated include power consumption, access delay, memory density, and scalability.The impact of power gating techniques on leakage current reduction and energy efficiency enhancement is also analyzed to maintain data integrity during idle periods.Challenges such as charge retention, threshold voltage variation, leakage control, and device variability at cryogenic temperatures are systematically addressed.Simulation results indicate that DRAM offers higher memory density and better energy efficiency at elevated frequencies, suited for large-scale cryogenic applications.SRAM delivers low-latency and high-reliability performance but with increased static power consumption and larger area overhead.These insights guide the design of next-generation cryo-CMOS memory solutions focused on achieving scalable, energy-efficient embedded memories for quantum computing and superconducting electronics.