Design And Implementation Of 2D FIR Filter Using Modified Adder And Multiplier

This project focuses on the design and implementation of a two-dimensional (2D) Finite Impulse Response (FIR) filter using Verilog, targeting a Spartan-6 FPGA for real-time image processing applications.The objective is to enhance computational efficiency and optimize hardware utilization by addressing limitations found in conventional FIR filter architectures, such as high propagation delays caused by ripple carry adders (RCA).To improve performance, the proposed system replaces the RCA with a compressor adder and evaluates two architectural variations-one using sequential processing without data broadcasting and another employing parallel processing with data broadcasting.The design is synthesized and simulated using Xilinx Vivado and evaluated across multiple configurations (3-tap, 6-tap, and 12-tap).Experimental results demonstrate that the data broadcast architecture, in conjunction with the compressor adder, significantly improves processing speed and reduces power consumption without increasing logic utilization.The proposed system presents a scalable and efficient solution suitable for high-performance digital filtering applications in real-time environments.