Energy-Efficient VLSI Hardware Accelerators for Real-Time Image and Multimedia Signal Processing Applications

mage and multimedia signal processing applications that require processing in real time are also being deployed on energy-restrained embedded and edge systems, where traditional CPU- and GPU-based application choices are no longer capable of satisfying hard power and latency constraints. Specialised VLSI hardware accelerators offer an efficient alternative, but it is difficult to attain a high level of energy efficiency with a requirement of real-time performance with such high overheads of data movement and memory access. The paper introduces a unified energy and performance co-design methodology, which was used to develop an energy-efficient VLSI hardware accelerator of the real-time image and multimedia signal processing. A computation, memory, and control energy analytical model to system level is used to make architectural decisions with explicit throughput assuming constraints. The accelerator proposed combines an array of parallel processing elements, hierarchical on-chip memory and a dataflow adaptable control to limit off-chip accesses. The minimization of data reuse and low-power design methods is another method to save energy. Representative image and multimedia kernel experimental evaluation shows higher energy efficiency and through put than state of the art designs with deadlines being met.