Real-Time and Low-Latency VLSI Implementations of Deep Learning-Based Signal Processing Algorithms

The recent establishment of deep learning (DL) methods in contemporary signal processing systems such as biomedical monitoring, radar sensing, speech enhancement, and image and multimedia processing has presented a high demand on real-time criteria, delay, throughput, and power use. Software-based realizations of deep neural networks are also notorious in embedded and edge development platforms, even though they can be used to achieve high accuracy inference, because of the erratic latency and high power consumption. This paper is an attempt to solve these problems by proposing a hardware-friendly VLSI implementation scheme of a deep learning-based signal processing algorithm to operate at real-time, and low-latency. The methodology proposed uses a hardware conscious deep neural network model directed into a parallel and pipelined architecture of VLSI that uses both data and task parallelism. An optimized processor elements that is combined with a streaming dataflow model, and localized memory buffering is employed to minimize end to end inference latency as well as overhead in accessing memory. The architecture will be in such a way that it allows running continuous signal processing in a very strict real-time setup and still be scalable in terms of resources. The suggested framework is tested and executed in an FPGA platform by applying post-synthesis and post-implementation analysis. It was also shown that experimental observations showed significant reduction of latency, throughput increase and reduced power consumption in contrast to a baseline non-optimized version of the same deep learning model. The results prove that hardware-software co-designing is a critical component to implement deep learning-based signal processing systems in real-time embedded systems. The suggested VLSI architecture will offer a feasible answer to the challenge of low-latency, low-energy-consuming intelligent signal processing in the next-generation edge and cyber-physical systems.