BiN-EdgePruning: edge pruning based on biased neighborhoods for printed circuit netlists

Automatic schematic generation is a key aspect of reverse engineering for printed circuit boards, and its cost is usually proportional to the size of the circuit. The generation of schematics for large-scale, realistic netlists poses a significant challenge within this domain. Netlist partitioning is a major approach to addressing this challenge. It reduces the cost of schematic generation by segmenting netlists into sub-netlists of moderate size based on their functional modules. Traditional methods that utilize expert systems for netlist partitioning exhibit high sensitivity to parameters and demonstrate poor adaptability across different netlists. Furthermore, their experimental data are typically constructed manually, making them difficult to reproduce. To address these limitations, this article first presents a set of graph datasets designed specifically for netlist partitioning experiments. Second, to tackle the neighborhood bias problem prevalent in real circuit netlists, we propose a novel neighborhood bias edge pruning algorithm called BiN-EdgePruning. Building on this foundation, we integrate BiN-EdgePruning with graph convolutional networks to achieve end-to-end netlist partitioning, thereby eliminating the need for unnecessary parameter tuning. Experimental results demonstrate that the proposed pruning algorithm significantly enhances the accuracy of printed circuit netlist partitioning across various graph neural network architectures.