On-Chip Programmable Traffic Injection for Flexible Cache Coherence Validation

Cache coherence implementing memory consistency is a transversal feature of most MPSoCs. However, cache coherence validation is challenging due to the limited observability and controllability available for at-speed testing. This is particularly problematic for safety- and security-critical domains, whose risk of failure must be proven to be residual.This paper presents a solution to simplify V&V of cache coherence implementation at hardware level by integrating a programmable traffic generator, hence overriding the limitations of regular software-based tests for at-speed testing. In particular, we build on SafeTI, an open source programmable and cycle-accurate traffic generator, to assess data consistency between the first two cache levels of a space-relevant platform based on Frontgrade Gaisler's IPs.