Design and optimization of ASCON-128/128a hardware accelerator for the Internet of Things

Lightweight authenticated encryption for IoT and embedded systems must ensure confidentiality and integrity while minimizing area and power consumption. This project implements hardware acceleration and optimization for ASCON-128/128a based on the NIST ASCON standard, incorporating modeling, simulation, and synthesis throughout the entire process using Synopsys VCS/Verdi and Design Compiler. The highlights of this design are the introduction of key masking to enhance resistance to side-channel attacks, pipelined processing to improve system throughput, and a bus interface designed at the system level for better access to the SOC. Compared to the initial version, the improved design achieves a fourfold increase in throughput while maintaining nearly identical performance at 720 MHz . However, it also results in approximately a fivefold increase in area and power consumption, with power reaching 15.96mW and area expanding to 45,433um^2 . Comparisons with the other two variants demonstrate that removing area constraints can provide greater performance benefits, but it also results in higher power consumption and larger area. Clock gating reduces power use and saves space. In real-world applications, constraints can be tailored to meet specific needs.