Verwendung von maschinellem Lernen zur frühen Abschätzung des zeitlichen Verhaltens beim Entwurf digitaler Schaltungen
Abstract
This thesis introduces the use of ML for timing estimation of digital ASIC designs at register transfer level. It integrates an RTL generation framework for automatic design collection, open-source EDA tools for gathering timing data of the designs in the training dataset, and ML techniques to learn from those datasets and predict timing-related metrics of new designs. The goal is to provide a rapid timing estimation of an RTL design without the need for synthesis and timing analysis tools.
Fields of Study & Subjects
VLSI and FPGA Design Techniques
Low-power high-performance VLSI design
Embedded Systems Design Techniques
Publication details
- Journal / source
- mediaTUM (Technical University of Munich)
- Publication date
- 12 January 2026
- Language
- EN
- Document type
- Thesis