Design and analysis of an ultra-low quiescent current capless LDO with fast transient response

This paper presents a fully integrated, capacitor-less low-dropout (CL-LDO) regulator tailored for battery-powered IoT applications, where simultaneously achieving ultra-low quiescent current and fast transient response remains challenging. The proposed LDO, implemented in a GF 55 nm CMOS process and evaluated in Cadence Spectre, adopts an adaptive architecture that switches between a two-stage topology at light load and a three-stage topology at heavy load to balance power and bandwidth. At light load, classic Miller compensation ensures pole separation and stability; at heavy load, an inherent feed-forward path introduces a left-half-plane zero that cancels the most detrimental non-dominant pole, maintaining robust stability across operating modes. Simulation results demonstrate 12 nA quiescent current at no load, while the adaptive biasing keeps the peak quiescent current below 8.85 µA over the load range. The regulator achieves a load regulation of 0.104% and a line regulation of 0.0073%. Under typical conditions (TT, 27 °C, 2.5 V), load-step tests show rapid recovery, settling within 210 ns for a rising step and 230 ns for a falling step, confirming strong dynamic performance without external capacitors. Overall, the proposed CL-LDO reconciles nanoampere-level quiescent power with sub-microsecond transient recovery, offering a practical and scalable solution for highly integrated, low-power power management ICs (PMICs).