VeriPy and ChatGPT-Aided VeriPy: A Compatible, Extensible, and Comprehensive Python-Based High-Level Synthesis Framework for Readable and Optimisable Hardware Generation

Field-Programmable Gate Arrays (FPGAs) are widely adopted in domains such as Artificial Intelligence (AI) and Software-Defined Radio (SDR) due to their reconfigurability and inherent parallelism. However, existing High-Level Synthesis (HLS) tools still suffer from major limitations, including rigid coding styles, limited transparency of generated hardware, restricted low-level control, and suboptimal performance caused by conservative compiler-driven scheduling and optimisation. These issues contribute to a persistent gap between software-oriented development and efficient hardware implementation. This thesis addresses these challenges through the development of VeriPy and ChatGPT-Aided VeriPy, two Python-based HLS frameworks that prioritise explicit hardware intent, structural transparency, controllable optimisation, and stable use of generative AI. Unlike conventional HLS tools that rely heavily on automated scheduling and opaque intermediate representations, VeriPy adopts a deterministic Python-to-Verilog translation methodology that preserves algorithmic structure and exposes parallelism explicitly. Performance improvements are achieved through user-controlled unrolling and pipelining, fine-grained mapping of operations to hardware primitives, and the generation of lean, modular Verilog that enables effective downstream synthesis and timing optimisation. An extensible hardware library further promotes modular reuse of verified building blocks, reducing over-generalisation and inefficiencies common in traditional HLS flows. ChatGPT-Aided VeriPy extends this approach by automatically restructuring standard Python code into VeriPy-compatible, hardware-aware representations, significantly reducing coding effort without changing the underlying hardware mapping strategy. By constraining generative AI to front-end code transformation and retaining deterministic backend generation, the framework ensures stability and repeatability. Experimental results show that VeriPy achieves up to 147% higher maximum frequency and 5700% higher throughput than Vivado HLS 2024 on selected benchmarks, with competitive resource usage. ChatGPT-Aided VeriPy reduces code length by up to 88% while maintaining equivalent performance. Overall, this work bridges the software–hardware gap without sacrificing hardware efficiency.