Ultra Düşük Gecikmeli Makine Öğrenimi için FPGA Donanım Hızlandırıcı: Yüksek Hızlı Ticaret için Mimari ve Sistem Seviyesinde İmplementasyonu

Mid-price prediction with ultra-low latency is a fundamental component in High Frequency Trading (HFT). This thesis explores the realization of XGBoost machine learning models on FPGA to achieve accurate predictions within sub-microsecond latency for HFT applications. To this end, model features are generated with integer semantics by construction, avoiding floating-point definitions, runtime normalization, and division operations. The XGBoost model is realized using a fully unrolled, LUT-based RTL implementation. Unlike existing LUT-based decision tree architectures, the proposed approach supports signed features and regression XGBoost model conversions, extending LUT-based inference beyond classification-only and unsigned-feature assumptions. The outcome of the thesis is a hardware-aware framework for low-latency, end-to-end deployment of XGBoost models on FPGA platforms. Unlike prior work limited to training or isolated inference, this thesis realizes a complete end-to-end system with hardware-based feature generation, for which no directly comparable implementations exist. The framework operates directly on reconstructed Limit Order Book (LOB) streams and incorporates hardware-oriented feature generation methodology, structured feature representation, and an automated flow for generating synthesizable hardware descriptions from LOB data. The framework is evaluated in terms of prediction accuracy, hardware resource consumption, and inference latency using an end-to-end FPGA realization. The results demonstrate that the proposed framework enables deterministic, sub-microsecond end-to-end inference on FPGA while preserving the behavior of the corresponding software model, enabling reliable deployment of machine learning–based mid-price prediction in latency-critical HFT systems.