Design of a 28-GHz RF power amplifier based on 55-nm CMOS technology

This dissertation presents a 28-GHz RF power amplifier (PA) based on 55-nm CMOS technology, tailored for 5G/6G millimeter-wave communication systems where high output power, high efficiency, and wide voltage adaptability are critical. The proposed PA adopts a three-way parallel 2-stacked topology, combining stacked voltage division and parallel power combining to overcome CMOS transistors’ low voltage tolerance and single-path power bottlenecks. A conjugate matched T-type interstage matching network minimizes signal reflection, while optimized biasing and harmonic suppression balance efficiency and linearity. Simulation results show a Gain of 22.2 dB, a Psat of 23.14 dBm, a peak PAE of 31.89%, and an OIP3 of 30.34 dBm. This PA operates stably across a 1.8–3.2 V supply voltage range, meeting key performance requirements for high-integration, low-cost millimeter-wave communication systems. Overall, the proposed PA achieves dual excellent performance of high efficiency and high linearity. Offering a feasible design approach for developing low-cost and high-performance power amplifiers.