Design and implementation of a control strategy for clock synchronization in PTP networks

This thesis presents the design, implementation, and validation of a high-precision clock syn- chronization strategy for automotive Ethernet networks following the IEEE 802.1AS (gPTP) profile. The primary objective of this research is to transform a standard Ethernet Capture Module into a time-aware synchronization node capable of sub-microsecond accuracy, a crit- ical requirement for modern Time-Sensitive Network (TSN) applications. The development process began with the mathematical modeling of the hardware Phase Ac- cumulator (PA) and the characterization of the system dynamics in discrete time. To regulate the local clock, a control architecture based on Proportional-Integral (PI) compensators was designed and initially validated through Simulink environments. A significant portion of this work focuses on the evolution from a Multi-Rate architecture to a Single-Rate approach. The latter addresses the instabilities inherent in non-periodic network message arrival by utilizing a linear interpolator, effectively decoupling the controller execution from the network rate. Experimental validation conducted on real hardware facilitated a comprehensive study of the synchronization sources of error. By analyzing the system’s performance, a distinction was es- tablished between deterministic static errors, originating from the hardware processing pipeline, and stochastic dynamic ones introduced by network jitter and quantization effects. This investi- gation provides a foundation for systematic error mitigation, demonstrating that the proposed single-rate architecture maintains high stability and robustness, making it an effective and scal- able solution in demanding automotive environments.