Nieuwe geheugentopologieën mogelijk gemaakt door IGZO in de BEOL en FeRAM-onderzoek voor DRAM-toepassingen

Recently, DRAM has faced challenges in two key areas: the sustainability of device scaling and the need to address the demands of emerging applications such as artificial intelligence (AI) and high-performance computing (HPC), which differ significantly from traditional domains like PCs, servers, mobile devices, graphics, and commodity systems. First, in process nodes below 20nm, the scaling ratio of the technology feature size (F), of DRAM has decreased to below 20%, a significant slowdown compared to the ∼30% scaling ratio achieved in earlier technology nodes (>20nm). Second, with the advent of the AI era, the 'memory wall' has emerged as a critical bottleneck for AI and machine learning (ML) applications. Since Ousterhout's analysis in 1990 [Ousterhout, 1990], memory bandwidth has been identified as the primary hardware issue, failing to keep pace with the rapid increases in CPU bandwidth [McKee, 2004, Wulf and McKee, 1995]. This doctoral research addresses these challenges by exploring three key directions. • 2T0C-IGZO: Improvement of noise immunity at the storage node. • 2T0C-IGZO: High-density and low-power read operation enabled by the proposed HSA circuit. • FeRAM: Design Space Exploration as a DRAM Alternative. These findings demonstrate how materials and architectural innovations can address the scaling limitations of DRAM, paving the way for high-density, energy-efficient memory solutions tailored to the demands of modern AI and HPC applications.